A reconfigurable hardware-software iteration co-synthesis algorithm based on vertex position tree

In reconfigurable computing, more tasks can be executed at a higher speed in hardware by time multiplexing with the limited area resources. Meanwhile, it also brings new challenges to the traditional hardware-software codesign. For offline scheduling, centralized shared structure reconfigurable platform, the ICS-VPT (iteration co-synthesis based on vertex position tree) algorithm synthesized hardware-software partitioning, hardware placement and task scheduling to improve system performance: The VPT (vertex position tree) data structure was first proposed, which could find a placement position quickly with small storage space; The ICS (iteration co-synthesis) algorithm grouped tasks according to data dependence graph and obtained the hardware/software tasks priorities by combining the communication cost, thus obtaining a reasonable partitioning and scheduling. Experimental results show that the ICS-VPT algorithm maintains a lower level of system running time by means of efficient reconfigurable resource management and flexible communication cost handling.